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M
PIC16F84A
Pin Diagrams
PDIP, SOIC
RA2 RA3 RA4/T0CKI MCLR VSS RB0/INT RB1 RB2 RB3
*1
18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
Devices Included in this Data Sheet:
* PIC16F84A * Extended voltage range device available (PIC16LF84A)
18 17 16 15 14 13 12 11 10
RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
High Performance RISC CPU Features:
* Only 35 single word instructions to learn * All instructions single cycle except for program branches which are two-cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * 1024 words of program memory * 68 bytes of data RAM * 64 bytes of data EEPROM * 14-bit wide instruction words * 8-bit wide data bytes * 15 special function hardware registers * Eight-level deep hardware stack * Direct, indirect and relative addressing modes * Four interrupt sources: - External RB0/INT pin - TMR0 timer overflow - PORTB<7:4> interrupt on change - Data EEPROM write complete
2 3 4 5 6 7 8 9
SSOP
RA2 RA3 RA4/T0CKI MCLR VSS VSS RB0/INT RB1 RB2 RB3
*1
PIC16F84A PIC16F84A
20 19 18 17 16 15 14 13 12 11
RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
2 3 4 5 6 7 8 9 10
Peripheral Features:
* 13 I/O pins with individual direction control * High current sink/source for direct LED drive - 25 mA sink max. per pin - 25 mA source max. per pin * TMR0: 8-bit timer/counter with 8-bit programmable prescaler
CMOS Enhanced Flash/EERPOM Technology:
* Low-power, high-speed technology * Fully static design * Wide operating voltage range: - Commercial: 2.0V to 5.5V - Industrial: 2.0V to 5.5V * Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 15 A typical @ 2V, 32 kHz - < 0.5 A typical standby current @ 2V
Special Microcontroller Features:
* 1000 erase/write cycles Enhanced Flash program memory * 1,000,000 typical erase/write cycles EEPROM data memory * EEPROM Data Retention > 40 years * In-Circuit Serial Programming (ICSPTM) - via two pins * Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Code-protection * Power saving SLEEP mode * Selectable oscillator options
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 1
PIC16F84A
Table of Contents
1.0 Device Overview ............................................................................................................................................................................ 3 2.0 Memory Organization..................................................................................................................................................................... 5 3.0 I/O Ports....................................................................................................................................................................................... 13 4.0 Timer0 Module ............................................................................................................................................................................. 17 5.0 Data EEPROM Memory............................................................................................................................................................... 19 6.0 Special Features of the CPU ....................................................................................................................................................... 21 7.0 Instruction Set Summary.............................................................................................................................................................. 33 8.0 Development Support .................................................................................................................................................................. 35 9.0 Electrical Characteristics for PIC16F84A..................................................................................................................................... 41 10.0 DC & AC Characteristics Graphs/Tables ..................................................................................................................................... 53 11.0 Packaging Information ................................................................................................................................................................. 55 Appendix A: Revision History ........................................................................................................................................................... 59 Appendix B: Conversion Considerations.......................................................................................................................................... 59 Appendix C: Migration from Baseline to Midrange Devices ............................................................................................................. 62 Index ................................................................................................................................................................................................... 63 On-Line Support................................................................................................................................................................................... 65 Reader Response ................................................................................................................................................................................ 66 PIC16F84A Product Identification System ........................................................................................................................................... 67
To Our Valued Customers
Most Current Data Sheet
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet. * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.
DS35007A-page 2
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
1.0 DEVICE OVERVIEW
This document contains device-specific information for the operation of the PIC16F84A device. Additional information may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023), which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F84A belongs to the mid-range family of the PICmicroTM microcontroller devices. A block diagram of the device is shown in Figure 1-1. The program memory contains 1K words, which translates to 1024 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 68 bytes. Data EEPROM is 64 bytes. There are also 13 I/O pins that are user-configured on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: * External interrupt * Change on PORTB interrupt * Timer0 clock input Table 1-1 details the pinout of the device with descriptions and details for each pin.
FIGURE 1-1:
PIC16F84A BLOCK DIAGRAM
13 Data Bus Program Counter 8 EEPROM Data Memory
Flash Program Memory PIC16F84A 1K x 14 Program Bus 8 Level Stack (13-bit) RAM File Registers PIC16F84A 68 x 8 7 RAM Addr
EEDATA
EEPROM Data Memory 64 x 8
14
EEADR
Instruction reg 5 Direct Addr
Addr Mux 7 Indirect Addr TMR0
FSR reg RA4/T0CKI STATUS reg 8
Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer W reg ALU
MUX 8 I/O Ports
RA3:RA0 RB7:RB1
Timing Generation
RB0/INT
OSC2/CLKOUT OSC1/CLKIN
MCLR
VDD, VSS
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 3
PIC16F84A
TABLE 1-1
Pin Name OSC1/CLKIN OSC2/CLKOUT
PIC16F84A PINOUT DESCRIPTION
DIP No. 16 15 SOIC No. 16 15 SSOP No. 18 19 I/O/P Type I O Buffer Type Description
ST/CMOS (3) Oscillator crystal input/external clock source input. -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.
MCLR
4
4
4
I/P
ST
RA0 RA1 RA2 RA3 RA4/T0CKI
17 18 1 2 3
17 18 1 2 3
19 20 1 2 3
I/O I/O I/O I/O I/O
TTL TTL TTL TTL ST Can also be selected to be the clock input to the TMR0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 VSS VDD Legend: I= input
6 7 8 9 10 11 12 13 5 14
6 7 8 9 10 11 12 13 5 14
7 8 9 10 11 12 13 14 5,6 15,16
I/O I/O I/O I/O I/O I/O I/O I/O P P
TTL/ST (1) TTL TTL TTL TTL TTL TTL/ST
(2)
RB0/INT can also be selected as an external interrupt pin.
Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins.
TTL/ST (2) -- --
O = output I/O = Input/Output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS35007A-page 4
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
2.0 MEMORY ORGANIZATION
FIGURE 2-1:
There are two memory blocks in the PIC16F84A. These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the "core" are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory, but is indirectly mapped. That is, an indirect address pointer specifies the address of the data EEPROM memory to read/write. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. More details on the EEPROM memory can be found in Section 5.0. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
PROGRAM MEMORY MAP AND STACK - PIC16F84A
PC<12:0> 13 CALL, RETURN RETFIE, RETLW Stack Level 1
* * *
Stack Level 8 Reset Vector Peripheral Interrupt Vector
0000h 0004h
User Memory Space
2.1
Program Memory Organization
3FFh
The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F84A, the first 1K x 14 (0000h-03FFh) are physically implemented (Figure 2-1). Accessing a location above the physically implemented address will cause a wraparound. For example, for locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h will be the same instruction. The reset vector is at 0000h and the interrupt vector is at 0004h.
1FFFh
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 5
PIC16F84A
2.2 Data Memory Organization
2.2.1 GENERAL PURPOSE REGISTER FILE The data memory is partitioned into two areas. The first is the Special Function Registers (SFR) area, while the second is the General Purpose Registers (GPR) area. The SFRs control the operation of the device. Portions of data memory are banked. This is for both the SFR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection. These control bits are located in the STATUS Register. Figure 2-1 shows the data memory map organization. Instructions MOVWF and MOVF can move values from the W register to any location in the register file ("F"), and vice-versa. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 2.4). Indirect addressing uses the present value of the RP0 bit for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The first twelve locations of each Bank are reserved for the Special Function Registers. The remainder are General Purpose Registers implemented as static RAM. Each General Purpose Register (GPR) is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 2.4). The GPR addresses in bank 1 are mapped to addresses in bank 0. As an example, addressing location 0Ch or 8Ch will access the same GPR.
FIGURE 2-1:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch
REGISTER FILE MAP PIC16F84A
File Address Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISA TRISB EECON1 EECON2(1) PCLATH INTCON 80h 81h 82h 83h 84h 85h 86h 87h EEDATA EEADR PCLATH INTCON 88h 89h 8Ah 8Bh 8Ch
Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB
68 General Purpose Registers (SRAM)
Mapped (accesses) in Bank 0
4Fh 50h
CFh D0h
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory location; read as '0'. Note 1: Not a physical register.
DS35007A-page 6
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (Figure 2-1 and Table 2-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature.
TABLE 2-1
REGISTER FILE SUMMARY
Value on Power-on Reset Value on all other resets (Note3)
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 0Ah 0Bh EECON1 EECON2 PCLATH INTCON INDF OPTION_REG PCL STATUS (2) FSR TRISA TRISB Uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 ---- ---1111 1111 0000 0000 PD Z DC C 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---- ---EEIF WRERR WREN WR RD ---0 x000 ---- ------0 0000 INTF RBIF 0000 000x ---- ---1111 1111 0000 0000 000q quuu uuuu uuuu ---1 1111 1111 1111 ---- ------0 q000 ---- ------0 0000 0000 000u EEDATA EEADR PCLATH INTCON INDF TMR0 PCL STATUS FSR PORTA (4) PORTB (5)
(2)
Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of the Program Counter (PC) IRP RP1 RP0 TO PD Z DC C
---- ---xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
---- ---uuuu uuuu 0000 0000 000q quuu uuuu uuuu ---u uuuu uuuu uuuu ---- ---uuuu uuuu uuuu uuuu ---0 0000 0000 000u
Indirect data memory address pointer 0 -- RB7 -- RB6 -- RB5 RA4/T0CKI RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0/INT
---x xxxx xxxx xxxx ---- ---xxxx xxxx xxxx xxxx
Unimplemented location, read as '0' EEPROM data register EEPROM address register -- GIE -- EEIE -- T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF INTF RBIF
---0 0000 0000 000x
Low order 8 bits of Program Counter (PC) IRP RP1 RP0 TO
Indirect data memory address pointer 0 -- -- -- PORTA data direction register
PORTB data direction register Unimplemented location, read as '0' -- -- --
EEPROM control register 2 (not a physical register) -- GIE -- EEIE -- T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred to PCLATH. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 4: On any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 7
PIC16F84A
2.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 7-2) because these instructions do not affect any status bit. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16F84A and should be programmed as cleared. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. Note 3: When the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. The specified bit(s) will be updated according to device logic
FIGURE 2-1:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) The IRP bit is not used by the PIC16F84A. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) Each bank is 128 bytes. Only bit RP0 is used by the PIC16F84A. RP1 should be maintained clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (for ADDWF and ADDLW instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note:For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
DS35007A-page 8
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
2.2.2.2 OPTION_REG REGISTER Note: When the prescaler is assigned to the WDT (PSA = '1'), TMR0 has a 1:1 prescaler assignment. The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-1:
R/W-1 RBPU bit7
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0
R/W-1 INTEDG
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to TMR0
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 9
PIC16F84A
2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources.
FIGURE 2-1:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0
R/W-0 EEIE
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Note: For the operation of the interrupt structure, please refer to Section *. EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT Interrupt Enable bit 1 = Enables the RB0/INT interrupt 0 = Disables the RB0/INT interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 has overflowed (must be cleared in software) 0 = TMR0 did not overflow INTF: RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred 0 = The RB0/INT interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS35007A-page 10
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
2.3 PCL and PCLATH 2.4
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.1 STACK
Indirect Addressing; INDF and FSR Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 2-1:
* * * *
INDIRECT ADDRESSING
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 06) * A read of the INDF register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
NEXT
movlw movwf clrf incf btfss goto :
CONTINUE
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-1. However, IRP is not used in the PIC16F84A.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 11
PIC16F84A
FIGURE 2-1: DIRECT/INDIRECT ADDRESSING
Direct Addressing RP1 RP0 (2) 6 from opcode 0 IRP (2) 7 Indirect Addressing (FSR) 0
bank select
location select
bank select
location select
00 00h
01 80h
0Bh 0Ch Data Memory (1) 4Fh 50h 7Fh Bank 0 Bank 1 Addresses map back to Bank 0
(3)
(3) FFh
Note 1: For memory map detail see Figure 2-1. 2: Maintain as clear for upward compatiblity with future products. 3: Not implemented.
DS35007A-page 12
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
3.0 I/O PORTS
FIGURE 3-1:
Data bus D WR Port Q VDD CK Q P
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
BLOCK DIAGRAM OF PINS RA3:RA0
Data Latch
3.1
PORTA and TRISA Registers
D WR TRIS Q
N
I/O pin
PORTA is a 5-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Note: On a Power-on Reset, these pins are configured as inputs and read as '0'.
VSS CK Q TTL input buffer
TRIS Latch
RD TRIS Q D
Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.
EN RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA4 as output TRISA<7:5> are always read as '0'.
STATUS, RP0 PORTA
BSF MOVLW
STATUS, RP0 0x0F
MOVWF
TRISA
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 13
PIC16F84A
FIGURE 3-2:
Data bus WR PORT
BLOCK DIAGRAM OF PIN RA4
D
Q Q
CK
N Data Latch VSS
D Q Q
RA4 pin
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q D EN EN
RD PORT TMR0 clock input Note: I/O pin has protection diodes to VSS only.
TABLE 3-1
Name RA0 RA1 RA2 RA3 RA4/T0CKI
PORTA FUNCTIONS
Bit0 bit0 bit1 bit2 bit3 bit4 Buffer Type TTL TTL TTL TTL ST Function
Input/output Input/output Input/output Input/output Input/output or external clock input for TMR0. Output is open drain type. Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2
Address 05h 85h Name PORTA TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- Bit 6 -- -- Bit 5 -- -- Bit 4 RA4/T0CKI TRISA4 Bit 3 RA3 TRISA3 Bit 2 RA2 TRISA2 Bit 1 RA1 TRISA1 Bit 0 RA0 TRISA0 Value on Power-on Reset ---x xxxx ---1 1111 Value on all other resets ---u uuuu ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS35007A-page 14
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
3.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
STATUS, RP0 PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-4:
RBPU(1)
BLOCK DIAGRAM OF PINS RB3:RB0
VDD weak P pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(2)
FIGURE 3-3:
BLOCK DIAGRAM OF PINS RB7:RB4
VDD
Data bus RBPU(1) Data Latch D CK TRIS Latch D WR TRIS CK Q TTL Input Buffer Q I/O pin(2) WR TRIS WR Port
weak P pull-up
Data bus WR Port
CK
TTL Input Buffer
RD TRIS Q RD Port D EN
RD TRIS
Latch Q D EN
RB0/INT Schmitt Trigger Buffer Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION_REG register). 2: I/O pins have diode protection to VDD and VSS. RD Port
RD Port Set RBIF From other RB7:RB4 pins
Q
D EN RD Port
Note 1: TRISB = '1' enables weak pull-up (if RBPU = '0' in the OPTION_REG register). 2: I/O pins have diode protection to VDD and VSS.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 15
PIC16F84A
TABLE 3-3
Name RB0/INT
PORTB FUNCTIONS
Bit bit0 Buffer Type TTL/ST(1) I/O Consistency Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger. Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4
Addr 06h 86h 81h Name PORTB TRISB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 TRISB5 T0CS Bit 4 RB4 TRISB4 T0SE Bit 3 RB3 TRISB3 PSA Bit 2 RB2 TRISB2 PS2 Bit 1 RB1 TRISB1 PS1 Bit 0 RB0/INT TRISB0 PS0 Value on Power-on Reset xxxx xxxx 1111 1111 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
OPTION_REG
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS35007A-page 16
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h Additional information on external clock requirements is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
4.2
Prescaler
Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler T0SE 3 PS2, PS1, PS0 T0CS PSA Set interrupt flag bit T0IF on overflow PSout Sync with Internal clocks (2 cycle delay) TMR0 PSout 8
RA4/T0CKI pin
0
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 17
PIC16F84A
4.2.1 SWITCHING PRESCALER ASSIGNMENT
4.3
Timer0 Interrupt
The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicroTM Mid-Range Reference Manual, DS3023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1
Address 01h 0Bh,8Bh 81h 85h
REGISTERS ASSOCIATED WITH TIMER0
Name TMR0 INTCON OPTION_REG TRISA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 --11 1111 Value on all other resets uuuu uuuu 0000 000u 1111 1111 --11 1111
Timer0 module's register GIE PEIE T0IE T0CS
RBPU INTEDG -- --
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS35007A-page 18
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
5.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory. These registers are: * * * * EECON1 EECON2 (Not a physically implemented register) EEDATA EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well as from chip to chip. Please refer to AC specifications for exact limits. When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory. Additional information on the Data EEPROM is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16F84A devices have 64 bytes of data EEPROM with an address range from 0h to 3Fh.
FIGURE 5-1:
U -- bit7 U --
EECON1 REGISTER (ADDRESS 88h)
U -- R/W-0 EEIF R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-x RD bit0 = Readable bit = Writable bit = Settable bit = Unimplemented bit, read as `0' - n = Value at POR reset R W S U
bit 7:5 bit 4
Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR reset or any WDT reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software). 0 = Does not initiate an EEPROM read
bit 3
bit 2
bit 1
bit 0
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 19
PIC16F84A
5.1 Reading the EEPROM Data Memory
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; therefore it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user (during a write operation). code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
EXAMPLE 5-1:
BCF MOVLW MOVWF BSF BSF BCF MOVF
DATA EEPROM READ
; ; ; ; ; ; ; Bank 0 Address to read Bank 1 EE Read Bank 0 W = EEDATA
STATUS, RP0 CONFIG_ADDR EEADR STATUS, RP0 EECON1, RD STATUS, RP0 EEDATA, W
5.3
Write Verify
5.2
Writing to the EEPROM Data Memory
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte.
Depending on the application, good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 5-1) to the desired value to be written. This should be used in applications where an EEPROM bit will be stressed near the specification limit. The Total Endurance disk will help determine your comfort level. Generally the EEPROM write failure will be a bit which was written as a '0', but reads back as a '1' (due to leakage off the bit).
EXAMPLE 5-1:
BSF BCF BSF MOVLW MOVWF MOVLW MOVWF BSF BSF
DATA EEPROM WRITE
; ; ; ; ; ; ; ; ; ; Bank 1 Disable INTs. Enable Write Write 55h Write AAh Set WR bit begin write Enable INTs. READ BSF EECON1, RD ; YES, Read the ; value written STATUS, RP0 ; Bank 0
Required Sequence
STATUS, RP0 INTCON, GIE EECON1, WREN 55h EECON2 AAh EECON2 EECON1,WR INTCON, GIE
EXAMPLE 5-1:
BCF : : MOVF BSF
WRITE VERIFY
Bank 0 Any code can go here Must be in Bank 0 Bank 1
STATUS, RP0 ; ; ; EEDATA, W ; STATUS, RP0 ;
The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected)
BCF ; ; Is the value written (in W reg) and ; read (in EEDATA) the same? ; SUBWF EEDATA, W ; BTFSS STATUS, Z ; Is difference 0? GOTO WRITE_ERR ; NO, Write error : ; YES, Good write : ; Continue program
TABLE 5-1
Address Name
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset xxxx xxxx xxxx xxxx EEIF WRERR WREN WR RD ---0 x000 ---- ---Value on all other resets uuuu uuuu uuuu uuuu ---0 q000 ---- ----
08h 09h 88h 89h
EEDATA EEADR EECON1 EECON2
EEPROM data register EEPROM address register -- -- --
EEPROM control register 2
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not used by data EEPROM.
DS35007A-page 20
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
6.0 SPECIAL FEATURES OF THE CPU
the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. This design keeps the device in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode offers a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer time-out or through an interrupt. Several oscillator options are provided to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select the various options. Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16F84A has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: * OSC Selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit serial programming The PIC16F84A has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep
6.1
Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. Address 2007h is beyond the user program memory space and it belongs to the special test/configuration memory space (2000h - 3FFFh). This space can only be accessed during programming.
FIGURE 6-1:
CONFIGURATION WORD - PIC16F84A
R/P-u CP R/P-u R/P-u R/P-u R/P-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit - n = Value at POR reset u = unchanged
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u CP CP CP CP CP CP CP CP CP bit13
bit 13:4 CP: Code Protection bit 1 = Code protection off 0 = All memory is code protected bit 3 PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 2
bit 1:0
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 21
PIC16F84A
6.2
6.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 6-1
Ranges Tested: Mode XT
CAPACITOR SELECTION FOR CERAMIC RESONATORS
The PIC16F84A can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz
OSC1/C1
OSC2/C2
HS
Note :
47 - 100 pF 47 - 100 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
6.2.2
In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 6-2).
Recommended values of C1 and C2 are identical to the ranges tested table. Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for the appropriate values of external components.
Resonators Tested:
FIGURE 6-2:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To internal logic SLEEP PIC16FXX
C1(1)
455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz
Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA10.00MTZ
0.3% 0.5% 0.5% 0.5% 0.5%
None of the resonators had built-in capacitors.
XTAL OSC2 C2(1) Note1: 2: 3: RS(2)
RF(3)
TABLE 6-2
Mode LP
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Freq 32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 4 MHz 10 MHz OSC1/C1 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF OSC2/C2 68 - 100 pF 15 - 33 pF 100 - 150 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF 15 - 33 pF
See Table 6-1 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen.
XT
HS
Note :
The PIC16F84A oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 6-3).
FIGURE 6-3:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16FXX Open OSC2
Higher capacitance increases the stability of oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. For VDD > 4.5V, C1 = C2 30 pF is recommended.
Crystals Tested: 32.768 kHz 100 kHz 200 kHz 1.0 MHz 2.0 MHz 4.0 MHz 10.0 MHz Epson C-001R32.768K-A Epson C-2 100.00 KC-P STD XTL 200.000 KHz ECS ECS-10-13-2 ECS ECS-20-S-2 ECS ECS-40-S-4 ECS ECS-100-S-4 20 PPM 20 PPM 20 PPM 50 PPM 50 PPM 50 PPM 50 PPM
Clock from ext. system
DS35007A-page 22
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
6.2.3 RC OSCILLATOR
6.3
Reset
For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) values, capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low Cext values. The user needs to take into account variation due to tolerance of the external R and C components. Figure 6-4 shows how an R/C combination is connected to the PIC16F84A.
The PIC16F84A differentiates between various kinds of reset: * * * * * Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP)
Figure 6-5 shows a simplified block diagram of the on-chip reset circuit. The MCLR reset path has a noise filter to ignore small pulses. The electrical specifications state the pulse width requirements for the MCLR pin. Some registers are not affected in any reset condition; their status is unknown on a POR reset and unchanged in any other reset. Most other registers are reset to a "reset state" on POR, MCLR or WDT reset during normal operation and on MCLR reset during SLEEP. They are not affected by a WDT reset during SLEEP, since this reset is viewed as the resumption of normal operation. Table 6-3 gives a description of reset conditions for the program counter (PC) and the STATUS register. Table 6-4 gives a full description of reset states for all registers. The TO and PD bits are set or cleared differently in different reset situations (Section 6.7). These bits are used in software to determine the nature of the reset.
FIGURE 6-4:
VDD Rext
RC OSCILLATOR MODE
OSC1 Cext VSS Fosc/4 Recommended values: OSC2/CLKOUT
Internal clock PIC16FXX
5 k Rext 100 k Cext > 20pF
FIGURE 6-5:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR WDT Module VDD rise detect VDD OST/PWRT OST 10-bit Ripple counter OSC1/ CLKIN PWRT On-chip RC OSC(1) 10-bit Ripple counter R Q Chip_Reset SLEEP WDT Time_Out Reset Power_on_Reset S
Enable PWRT
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
See Table 6-5
Enable OST
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 23
PIC16F84A
TABLE 6-3 RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up Interrupt wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu uuu1 0uuu
Legend: u = unchanged, x = unknown. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 6-4
RESET CONDITIONS FOR ALL REGISTERS
MCLR Reset during: - normal operation - SLEEP WDT Reset during normal operation uuuu uuuu ---- ---uuuu uuuu 0000h 000q quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---0 0000 0000 000u ---- ---1111 1111 0000h 000q quuu
(3)
Register
Address
Power-on Reset
Wake-up from SLEEP: - through interrupt - through WDT Time-out
W INDF TMR0 PCL STATUS FSR PORTA
(4) (5)
-- 00h 01h 02h 03h 04h 05h 06h 08h 09h 0Ah 0Bh 80h 81h 82h 83h 84h 85h 86h 88h 89h 8Ah 8Bh
xxxx xxxx ---- ---xxxx xxxx 0000h 0001 1xxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x ---- ---1111 1111 0000h 0001 1xxx xxxx xxxx ---1 1111 1111 1111 ---0 x000 ---- ------0 0000 0000 000x
uuuu uuuu ---- ---uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) ---- ---uuuu uuuu PC + 1 uuuq quuu(3) uuuu uuuu ---u uuuu uuuu uuuu ---0 uuuu ---- ------u uuuu uuuu uuuu(1)
PORTB
EEDATA EEADR PCLATH INTCON INDF OPTION_REG PCL STATUS FSR TRISA TRISB EECON1 EECON2 PCLATH INTCON
Legend: Note 1: 2: 3: 4: 5:
uuuu uuuu ---1 1111 1111 1111 ---0 q000 ---- ------0 0000 0000 000u
u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. One or more bits in INTCON will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). Table 6-3 lists the reset value for each specific condition. On any device reset, these pins are configured as inputs. This is the value that will be in the port output latch.
DS35007A-page 24
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
6.4 Power-on Reset (POR) FIGURE 6-6:
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A minimum rise time for VDD must be met for this to operate properly. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." The POR circuit does not produce an internal reset when VDD declines.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
VDD D
R R1 MCLR C PIC16FXX
6.5
Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a fixed 72 ms nominal time-out (TPWRT) from POR (Figure 6-7, Figure 6-8, Figure 6-9 and Figure 6-10). The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level (Possible exception shown in Figure 6-10). A configuration bit, PWRTE, can enable/disable the PWRT. See Figure 6-1 for the operation of the PWRTE bit for a particular device. The power-up time delay TPWRT will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details.
Note 1: External Power-on Reset circuit is required only if VDD power-up rate is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not exceed 0.2V (max leakage current spec on MCLR pin is 5 A). A larger voltage drop will degrade VIH level on the MCLR pin. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of an MCLR pin breakdown due to ESD or EOS.
6.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) after the PWRT delay ends (Figure 6-7, Figure 6-8, Figure 6-9 and Figure 6-10). This ensures the crystal oscillator or resonator has started and stabilized. The OST time-out (TOST) is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value. In this case (Figure 6-10), an external power-on reset circuit may be necessary (Figure 6-6).
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 25
PIC16F84A
FIGURE 6-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 6-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR
INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS35007A-page 26
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
FIGURE 6-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 6-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 27
PIC16F84A
6.7 Time-out Sequence and Power-down Status Bits (TO/PD) 6.8 Interrupts
The PIC16F84A has 4 sources of interrupt: * * * * External interrupt RB0/INT pin TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) Data EEPROM write complete interrupt
On power-up (Figure 6-7, Figure 6-8, Figure 6-9 and Figure 6-10) the time-out sequence is as follows: First PWRT time-out is invoked after a POR has expired. Then the OST is activated. The total time-out will vary based on oscillator configuration and PWRTE configuration bit status. For example, in RC mode with the PWRT disabled, there will be no time-out at all.
TABLE 6-5
Oscillator Configuration XT, HS, LP RC
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRT PWRT Enabled Disabled 72 ms + 1024TOSC 1024TOSC 72 ms -- Wake-up from SLEEP 1024TOSC --
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also contains the individual and global interrupt enable bits. The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. Bit GIE is cleared on reset. The "return from interrupt" instruction, RETFIE, exits interrupt routine as well as sets the GIE bit, which re-enable interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. When an interrupt is responded to; the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. For external interrupt events, such as the RB0/INT pin or PORTB change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for both one and two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid infinite interrupt requests. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit.
Since the time-outs occur from the POR reset pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high, execution will begin immediately (Figure 6-7). This is useful for testing purposes or to synchronize more than one PIC16F84A device when operating in parallel. Table 6-6 shows the significance of the TO and PD bits. Table 6-3 lists the reset conditions for some special registers, while Table 6-4 lists the reset conditions for all the registers.
TABLE 6-6
TO 1 0 x 0 0 1 1 PD 1 x 0 1 0 1 0
STATUS BITS AND THEIR SIGNIFICANCE
Condition Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset (during normal operation) WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
FIGURE 6-11: INTERRUPT LOGIC
T0IF T0IE INTF INTE RBIF RBIE EEIF EEIE GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
DS35007A-page 28
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
6.8.1 INT INTERRUPT 6.8.4 DATA EEPROM INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION_REG<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing control bit INTE (INTCON<4>). Flag bit INTF must be cleared in software via the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake the processor from SLEEP (Section 6.11) only if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether the processor branches to the interrupt vector following wake-up. 6.8.2 TMR0 INTERRUPT At the completion of a data EEPROM write cycle, flag bit EEIF (EECON1<4>) will be set. The interrupt can be enabled/disabled by setting/clearing enable bit EEIE (INTCON<6>) (Section 5.0).
6.9
Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save key register values during an interrupt (e.g., W register and STATUS register). This is implemented in software. Example 6-1 stores and restores the STATUS and W register's values. The User defined registers, W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS registers values. Example 6-1 does the following: a) b) c) d) e) Stores the W register. Stores the STATUS register in STATUS_TEMP. Executes the Interrupt Service Routine code. Restores the STATUS (and bank select bit) register. Restores the W register.
An overflow (FFh 00h) in TMR0 will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (Section 4.0). 6.8.3 PORB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<3>) (Section 3.2). Note 1: For a change on the I/O pin to be recognized, the pulse width must be at least TCY wide.
EXAMPLE 6-1:
PUSH MOVWF SWAPF MOVWF : : : : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP STATUS, W STATUS_TEMP ; ; ; : ; ; ; ; ; ; ; ; ; Copy W to TEMP register, Swap status to be saved into W Save status to STATUS_TEMP register Interrupt Service Routine should configure Bank as required Swap nibbles in STATUS_TEMP register and place result into W Move W into STATUS register (sets bank to original state) Swap nibbles in W_TEMP and place result in W_TEMP Swap nibbles in W_TEMP and place result into W
ISR
POP
STATUS_TEMP, W STATUS W_TEMP, F W_TEMP, W
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 29
PIC16F84A
6.10 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT Wake-up causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming configuration bit WDTE as a '0' (Section 6.1). 6.10.1 WDT PERIOD part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION_REG register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device RESET condition. The TO bit in the STATUS register will be cleared upon a WDT time-out. 6.10.2 WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to
It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs.
FIGURE 6-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 4-2)
0 WDT Timer
*
1
M U X
Postscaler 8 8 - to -1 MUX PS2:PS0
WDT Enable Bit
PSA
*
0 MUX 1
To TMR0 (Figure 4-2)
PSA
WDT Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 6-7
Addr Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PWRTE(1) PSA Bit 2 Bit 1 Bit 0 Value on Power-on Reset (2) 1111 1111 1111 1111 Value on all other resets
2007h 81h
Config. bits OPTION_REG
(2) RBPU
(2) INTEDG
(2) T0CS
(2) T0SE
WDTE PS2
FOSC1 PS1
FOSC0 PS0
Legend: x = unknown. Shaded cells are not used by the WDT. Note 1: See Figure 6-1 for operation of the PWRTE bit. 2: See Figure 6-1 and Section 6.12 for operation of the Code and Data protection bits.
DS35007A-page 30
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
6.11 Power-down Mode (SLEEP)
6.11.2 WAKE-UP FROM SLEEP A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 6.11.1 SLEEP The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. WDT Wake-up (if WDT was enabled). Interrupt from RB0/INT pin, RB port change, or data EEPROM write complete.
The Power-down mode is entered by executing the SLEEP instruction. If enabled, the Watchdog Timer is cleared (but keeps running), the PD bit (STATUS<3>) is cleared, the TO bit (STATUS<4>) is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). For the lowest current consumption in SLEEP mode, place all I/O pins at either at VDD or VSS, with no external circuitry drawing current from the I/O pins, and disable external clocks. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low.
Peripherals cannot generate interrupts during SLEEP, since no on-chip Q clocks are present. The first event (MCLR reset) will cause a device reset. The two latter events are considered a continuation of program execution. The TO and PD bits can be used to determine the cause of a device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). While the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
FIGURE 6-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note
1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 31
PIC16F84A
6.11.3 WAKE-UP USING INTERRUPTS
6.14
In-Circuit Serial Programming
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
PIC16F84A microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. Customers can manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product, allowing the most recent firmware or custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSPTM) Guide, (DS30277).
6.12
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
6.13
ID Locations
Four memory locations (2000h - 2004h) are designated as ID locations to store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable only during program/verify. Only the four least significant bits of ID location are usable.
DS35007A-page 32
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
7.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 7-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 7-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. Table 7-2 lists the instructions recognized by the MPASM assembler. Figure 7-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
FIGURE 7-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
TABLE 7-1
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
0
d
PC TO PD
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Program Counter Time-out bit Power-down bit
0
0
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s.
A description of each instruction is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 33
PIC16F84A
TABLE 7-2
Mnemonic, Operands
PIC16CXXX INSTRUCTION SET
Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS 14-Bit Opcode LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
DS35007A-page 34
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
8.0
8.1
DEVELOPMENT SUPPORT
Development Tools
8.3
ICEPIC: Low-Cost PICmicroTM In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * MPLABTM-ICE Real-Time In-Circuit Emulator * ICEPICTM Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * SIMICE * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C17 (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP) * KEELOQ(R) Evaluation Kits and Programmer
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through PentiumTM based machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation.
8.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
8.2
MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). MPLAB-ICE is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is available in two versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PICmicro MCU.
8.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 35
PIC16F84A
8.6 SIMICE Entry-Level Hardware Simulator 8.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip's simulator MPLABTM-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology's MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchip's PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicroTM 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entrylevel system development.
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
8.7
PICDEM-1 Low-Cost PICmicro Demonstration Board
8.9
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
DS35007A-page 36
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
8.10 MPLAB Integrated Development Environment Software 8.12 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
8.13
MPLAB-C17 Compiler
The MPLAB-C17 Code Development System is a complete ANSI `C' compiler and integrated development environment for Microchip's PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
8.14
Fuzzy Logic Development System (fuzzyTECH-MP)
8.11
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from MPLABICE, Microchip's Universal Emulator System. MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
8.15
SEEVAL(R) Evaluation and Programming System
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 37
PIC16F84A
8.16 KEELOQ(R) Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS35007A-page 38
Preliminary
(c) 1998 Microchip Technology Inc.
Software Tools
Programmers
Demo Boards
(c) 1998 Microchip Technology Inc.
TABLE 8-1:
PIC12C5XX Emulator Products
PIC14000
PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
MPLABTM-ICE
u
u
u
u
u
u
u
u
u
u
DEVELOPMENT TOOLS FROM MICROCHIP
ICEPICTM Low-Cost In-Circuit Emulator MPLABTM Integrated Development Environment MPLABTM C17* Compiler u u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
fuzzyTECH(R)-MP
Explorer/Edition Fuzzy Logic Dev. Tool Total EnduranceTM Software Model PICSTART(R)Plus Low-Cost Universal Dev. Kit PRO MATE(R) II Universal Programmer KEELOQ(R) Programmer SEEVAL(R) Designers Kit SIMICE PICDEM-14A PICDEM-1 PICDEM-2 PICDEM-3 KEELOQ(R) Evaluation Kit KEELOQ Transponder Kit u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u
Preliminary
DS35007A-page 39
u
u
u
u
u
u
u
u
u
u
u
u
u u
PIC16F84A
PIC16F84A
NOTES:
DS35007A-page 40
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
9.0 ELECTRICAL CHARACTERISTICS FOR PIC16F84A
Absolute Maximum Ratings Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS .......................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS(1) ...................................................................................................... -0.3 to +14V Voltage on RA4 with respect to VSS .......................................................................................................... -0.3 to +8.5V Total power dissipation(2) .....................................................................................................................................800 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................20 mA Maximum current sunk by PORTA ..........................................................................................................................80 mA Maximum current sourced by PORTA .....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB...................................................................................................................100 mA Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. Note 2: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 41
PIC16F84A
TABLE 9-1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16F84A-04
VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.0V to 5.5V 4.5 mA max. at 5.5V 14 A max. at 4V, WDT dis 4.0 MHz max. at 4V 4.0V to 5.5V 4.5 mA max. at 5.5V 14 A max. at 4V, WDT dis 4.0 MHz max. at 4V 4.5V to 5.5V 4.5 mA typ. at 5.5V 1.0 A typ. at 4.5V, WDT dis 4.0 MHz max. at 4.5V 4.0V to 5.5V 48 A typ. at 32 kHz, 2.0V 0.6 A typ. at 3.0V, WDT dis 200 kHz max. at 4V VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
OSC
RC
PIC16F84A-20
4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V, WDT dis 4..0 MHz max. at 4V 4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 5.5V, WDT dis 4.0 MHz max. at 4.5V 4.5V to 5.5V 10 mA max. at 5.5V typ. 1.0 A typ. at 4.5V, WDT dis 20 MHz max. at 4.5V VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq:
PIC16LF84A-04
2.0V to 5.5V 4.5 mA max. at 5.5V 7.0 A max. at 2V WDT dis 2.0 MHz max. at 2V 2.0V to 5.5V 4.5 mA max. at 5.5V 7.0 A max. at 2V WDT dis 2.0 MHz max. at 2V
XT
HS
Do not use in HS mode
LP
Do not use in LP mode
VDD: IDD: IPD: Freq:
2.0V to 5.5V 45 A max. at 32 kHz, 2.0V 7 A max. at 2.0V WDT dis 200 kHz max. at 2V
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
DS35007A-page 42
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
9.1 DC CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Min Typ Max Units Conditions 4.0 4.5 1.5* -- -- -- -- VSS 5.5 5.5 -- -- V V V V XT, RC and LP osc configuration HS osc configuration Device in SLEEP mode See section on Power-on Reset for details
DC Characteristics Power Supply Pins
Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Supply Current (Note 2)
D001 D001A D002* D003
D004* D004A*
SVDD
0.05* TBD
-- --
-- --
IDD D010 D010A
-- --
1.8 3
4.5 10
D013 D020 D021 D021A
IPD
Power-down Current (Note 3)
-- -- -- --
10 7.0 1.0 1.0
20 28 14 16
V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details RC and XT osc configuration (Note 4) mA FOSC = 4.0 MHz, VDD = 5.5V mA FOSC = 4.0 MHz, VDD = 5.5V (During Flash programming) HS osc configuration (PIC16F84A-20) FOSC = 20 MHz, VDD = 5.5V mA A VDD = 4.0V, WDT enabled, industrial A VDD = 4.0V, WDT disabled, commercial A VDD = 4.0V, WDT disabled, industrial
D022*
-- 6.0 20* A WDTE bit set, VDD = 4.0V, commercial -- -- 25* A WDTE bit set, VDD = 4.0V, extended * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD measurement.
Module Differential Current (Note 5) IWDT Watchdog Timer
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 43
PIC16F84A
9.2 DC CHARACTERISTICS: PIC16LF84A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Min Typ Max Units Conditions 2.0 1.5* -- -- -- VSS 5.5 -- -- V V V XT, RC, and LP osc configuration Device in SLEEP mode See section on Power-on Reset for details DC Characteristics Power Supply Pins
Parameter No.
Sym VDD VDR VPOR
Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Supply Current (Note 2)
D001 D002* D003
D004* D004A*
SVDD
0.05* TBD
-- --
-- --
IDD D010 D010A
-- --
1 3
4 10
D014 D020 D021 D021A IPD Power-down Current (Note 3)
-- -- -- --
15 3.0 0.4 0.4
45 16 7.0 9.0
V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details RC and XT osc configuration (Note 4) mA FOSC = 2.0 MHz, VDD = 5.5V mA FOSC = 2.0 MHz, VDD = 5.5V (During Flash programming) LP osc configuration FOSC = 32 kHz, VDD = 2.0V, A WDT disabled A VDD = 2.0V, WDT enabled, industrial A VDD = 2.0V, WDT disabled, commercial A VDD = 2.0V, WDT disabled, industrial
D022*
-- 6.0 20* A WDTE bit set, VDD = 4.0V, commercial -- -- 25* A WDTE bit set, VDD = 4.0V, industrial * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD measurement.
Module Differential Current (Note 5) IWDT Watchdog Timer
DS35007A-page 44
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
9.3 DC CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial) PIC16LF84A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 9.1 and Section 9.2.
DC Characteristics All Pins Except Power Supply Pins
Parameter No.
Sym VIL
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, RA4/T0CKI OSC1 (XT, HS and LP modes) OSC1 (RC mode) Input High Voltage I/O ports with TTL buffer
Min
Typ
Max
Units
Conditions
D030 D030A D031 D032 D033 D034 VIH D040 D040A D041 D042 D043 D043A D050 D070
VSS VSS VSS Vss Vss Vss
-- -- -- -- -- -- --
0.8 0.16VDD 0.2VDD 0.2VDD 0.3VDD 0.1VDD
V V V V V V
4.5V VDD 5.5V (Note 4) entire range (Note 4) entire range (Note 1)
VHYS IPURB
D060 D061 D063 *
IIL
with Schmitt Trigger buffer MCLR, RA4/T0CKI OSC1 (XT, HS and LP modes) OSC1 (RC mode) Hysteresis of Schmitt Trigger inputs PORTB weak pull-up current Input Leakage Current (Note 2,3) I/O ports MCLR, RA4/T0CKI OSC1
2.0 0.25VDD +0.8 0.8 VDD 0.8 VDD 0.7 VDD 0.9 VDD
--
-- -- -- -- --
VDD VDD VDD VDD VDD VDD
--
V V
4.5V VDD 5.5V (Note 4) entire range (Note 4) entire range
0.1 250*
V V V V A
(Note 1)
50*
400*
VDD = 5.0V, VPIN = VSS
-- -- --
-- -- --
1 5 5
A A A
Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F84A with an external clock while the device is in RC mode, or chip damage may result. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: The user may choose the better of the two specs.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 45
PIC16F84A
9.4 DC CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial) PIC16LF84A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating voltage VDD range as described in DC spec Section 9.1 and Section 9.2. Min Typ Max Units Conditions
DC Characteristics All Pins Except Power Supply Pins
Parameter No.
Sym
Characteristic Output Low Voltage I/O ports OSC2/CLKOUT Output High Voltage I/O ports (Note 3) OSC2/CLKOUT (Note 3)
D080 D083
VOL
-- --
-- --
0.6 0.6
V V
IOL = 8.5 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, (RC Mode Only) IOH = -3.0 mA, VDD = 4.5V IOH = -1.3 mA, VDD = 4.5V (RC Mode Only)
D090 D092
VOH
VDD-0.7 VDD-0.7
-- --
-- --
V V
D150
VOD
D100
Open Drain High Voltage RA4 pin Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
--
--
8.5
V
--
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
CIO
All I/O pins and OSC2 (RC mode) Data EEPROM Memory Endurance VDD for read/write Erase/Write cycle time Program Flash Memory Endurance VDD for read
--
--
50
pF
D120 D121 D122 D130 D131
ED VDRW TDEW EP VPR
1M* VMIN -- 100* VMIN
10M
--
--
5.5 8*
--
4 1000
--
E/W 25C at 5V V VMIN = Minimum operating voltage ms E/W V VMIN = Minimum operating voltage V ms
5.5
-- D132 VPEW VDD for erase/write 4.5 5.5 D133 TPEW Erase/Write cycle time -- 4 8 * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F84A with an external clock while the device is in RC mode, or chip damage may result. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: The user may choose the better of the two specs.
DS35007A-page 46
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
9.5
9.5.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time io I/O port inp INT pin mc MCLR Uppercase symbols and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
os,osc ost pwrt rbt t0 wdt
OSC1 oscillator start-up timer power-up timer RBx pins T0CKI watchdog timer
P R V Z
Period Rise Valid High Impedance
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 47
PIC16F84A
9.5.2 TIMING CONDITIONS The temperature and voltages specified in Table 9-2 apply to all timing specifications unless otherwise noted. All timings are measure between high and low measurement points as indicated in Figure 9-1. Figure 9-2 specifies the load conditions for the timing specifications.
TABLE 9-2
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial -40C TA +85C for industrial Operating voltage VDD range as described in DC spec Section 9.1 and Section 9.2
AC CHARACTERISTICS
FIGURE 9-1:
PARAMETER MEASUREMENT INFORMATION
0.7 VDD XTAL 0.8 VDD RC (High) 0.3 VDD XTAL 0.15 VDD RC (Low) 0.9 VDD (High) 0.1 VDD (Low) I/O Port Measurement Points
OSC1 Measurement Points
FIGURE 9-2:
LOAD CONDITIONS
Load Condition 1 VDD/2 RL Pin VSS CL Pin VSS CL Load Condition 2
RL = CL =
464 50 pF 15 pF for all pins except OSC2. for OSC2 output.
DS35007A-page 48
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
9.5.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 9-3:
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 9-3
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC DC DC DC 0.1 0.1 1.0 DC 500 250 100 5.0 500 250 500 250 100 5.0 0.4 60 * 50 * 2.0 * 35 * 25 * 50 * 15 * Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4/Fosc -- -- -- -- -- -- -- Max 2 4 20 200 2 4 2 4 20 200 -- -- -- -- -- -- 10,000 10,000 1,000 -- DC -- -- -- -- -- -- -- Units MHz MHz MHz kHz MHz MHz MHz MHz MHz kHz ns ns ns s ns ns ns ns ns s s ns ns s ns ns ns ns Conditions XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc XT, RC osc XT, RC osc HS osc LP osc RC osc RC osc XT osc XT osc HS osc LP osc XT osc XT osc LP osc HS osc XT osc LP osc HS osc (-04, LF) (-04) (-20) (-04, LF) (-04, LF) (-04) (-04, LF) (-04) (-20) (-04, LF) (-04, LF) (-04) (-20) (-04, LF) (-04, LF) (-04) (-04, LF) (-04) (-20) (-04, LF) (-04, LF) (-04) (-04, LF) (-20) (-04) (-04, LF) (-20)
Oscillator Frequency(1)
1
Tosc
External CLKIN Period(1)
Oscillator Period(1)
2 3
TCY TosL, TosH
Instruction Cycle Time(1) Clock in (OSC1) High or Low Time
4
TosR, TosF
Clock in (OSC1) Rise or Fall Time
These parameters are characterized but no tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
*
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 49
PIC16F84A
FIGURE 9-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 22 23 12 18 16 Q1 Q2 11 Q3
20, 21 Note: All tests must be done with specified capacitive loads (Figure 9-2) 50 pF on I/O pins and CLKOUT.
TABLE 9-4
Parameter No. 10 10A 11 11A 12 12A 13 13A 14 15 16 17 18 TckF TckR
CLKOUT AND I/O TIMING REQUIREMENTS
Sym TosH2ckL Characteristic OSC1 to CLKOUT Standard Extended (LF) TosH2ckH OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI CLKOUT to Port out valid Port in valid before CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time Trbp RB7:RB4 change INT high or low time Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) TioF Tinp Standard Extended (LF) Standard Extended (LF) Standard Extended (LF) Min -- -- -- -- -- -- -- -- -- 0.30TCY + 30 * 0.30TCY + 80 * 0* -- -- 10 * 10 * -75 * -175 * -- -- -- -- 20 * 55 * TOSC TOSC Typ 15 15 15 15 15 15 15 15 -- -- -- -- -- -- -- -- -- -- 10 10 10 10 -- -- -- -- Max 30 * 120 * 30 * 120 * 30 * 100 * 30 * 100 * 0.5TCY +20 * -- -- -- 125 * 250 * -- -- -- -- 35 * 70 * 35 * 70 * -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Port in hold after CLKOUT
19
TioV2osH
20 20A 21 21A 22 22A 23 23A *
TioR
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. By design Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS35007A-page 50
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
FIGURE 9-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR 30 Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins 32
31 34
TABLE 9-5
Parameter No. 30 31 32 33 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or reset 28 * -- Min 2* 7* Typ -- 18 1024TOSC 72 -- 132 * 100 * Max -- 33 * Units s ms ms ms ns Conditions
VDD = 5.0V, extended VDD = 5.0V, extended
TOSC = OSC1 period
VDD = 5.0V, extended
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 51
PIC16F84A
FIGURE 9-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 9-6
Parameter No. 40
TIMER0 CLOCK REQUIREMENTS
Sym Characteristic Min 0.5TCY + 20 * 50 * 30 * 0.5TCY + 20 * 50 * 20 * TCY + 40 * N Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns 2.0V VDD 3.0V 3.0V VDD 6.0V N = prescale value (2, 4, ..., 256) 2.0V VDD 3.0V 3.0V VDD 6.0V Conditions
Tt0H T0CKI High Pulse Width No Prescaler With Prescaler
41
Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler
42 *
Tt0P T0CKI Period
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS35007A-page 52
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
10.0 DC & AC CHARACTERISTICS GRAPHS/TABLES
No data available at this time.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 53
PIC16F84A
NOTES:
DS35007A-page 54
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
11.0
11.1
PACKAGING INFORMATION
Package Marking Information
18L PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX AABBCDE
Example
PIC16F84A-04I/P 9832SAW
18L SOIC
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX
Example
PIC16F84A-04 /SO
AABBCDE
9848SAN
20L SSOP
XXXXXXXXXX XXXXXXXXXX
Example
PIC16F84A20/SS
AABBCDE
9822CAN
Legend: MM...M XX...X AA BB C
D E Note:
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5" Line S = 6" Line H = 8" Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 55
PIC16F84A
11.2 K04-007 18-Lead Plastic Dual In-line (P) - 300 mil
E
D
2 n E1 A1 A R c A2 B1 eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
1
L
B
p
MIN n p B B1 R c A A1 A2 L D E E1 eB
INCHES* NOM 0.300 18 0.100 0.013 0.018 0.055 0.060 0.000 0.005 0.005 0.010 0.110 0.155 0.075 0.095 0.000 0.020 0.125 0.130 0.890 0.895 0.245 0.255 0.230 0.250 0.310 0.349 5 10 5 10
MAX
MIN
0.023 0.065 0.010 0.015 0.155 0.115 0.020 0.135 0.900 0.265 0.270 0.387 15 15
MILLIMETERS NOM MAX 7.62 18 2.54 0.33 0.46 0.58 1.40 1.52 1.65 0.00 0.13 0.25 0.13 0.25 0.38 2.79 3.94 3.94 1.91 2.41 2.92 0.00 0.51 0.51 3.18 3.30 3.43 22.61 22.73 22.86 6.22 6.48 6.73 5.84 6.35 6.86 7.87 8.85 9.83 5 10 15 5 10 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS35007A-page 56
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
11.3 K04-051 18-Lead Plastic Small Outline (SO) - Wide, 300 mil
E1 p E
D
2 B n X 45 1
L R2
c A R1 Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
A1
L1
A2 MILLIMETERS NOM MAX 1.27 18 2.64 2.36 2.50 1.73 1.22 1.47 0.28 0.10 0.19 11.73 11.43 11.58 7.59 7.42 7.51 10.64 10.01 10.33 0.74 0.25 0.50 0.25 0.13 0.13 0.25 0.13 0.13 0.53 0.28 0.41 4 8 0 0.51 0.25 0.38 0.30 0.23 0.27 0.48 0.36 0.42 0 12 15 0 12 15
MIN p n A A1 A2 D E E1 X R1 R2 L L1 c B
INCHES* NOM 0.050 18 0.093 0.099 0.048 0.058 0.004 0.008 0.450 0.456 0.292 0.296 0.394 0.407 0.010 0.020 0.005 0.005 0.005 0.005 0.016 0.011 0 4 0.015 0.010 0.011 0.009 0.017 0.014 0 12 0 12
MAX
MIN
0.104 0.068 0.011 0.462 0.299 0.419 0.029 0.010 0.010 0.021 8 0.020 0.012 0.019 15 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 57
PIC16F84A
11.4 K04-072 20-Lead Plastic Shrink Small Outine (SS) - 5.30 mm
E1 E p
D
B n
2 1 L R2
c
A A1 R1 L1 A2
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
MIN p n A A1 A2 D E E1 R1 R2 L L1 c B
INCHES NOM 0.026 20 0.073 0.068 0.026 0.036 0.002 0.005 0.278 0.283 0.205 0.208 0.301 0.306 0.005 0.005 0.005 0.005 0.015 0.020 0 4 0.000 0.005 0.005 0.007 0.010 0.012 0 5 0 5
MAX
MIN
0.078 0.046 0.008 0.289 0.212 0.311 0.010 0.010 0.025 8 0.010 0.009 0.015 10 10
MILLIMETERS* NOM MAX 0.65 20 1.73 1.86 1.99 0.66 0.91 1.17 0.05 0.13 0.21 7.07 7.20 7.33 5.20 5.29 5.38 7.65 7.78 7.90 0.13 0.13 0.25 0.13 0.13 0.25 0.38 0.51 0.64 0 4 8 0.00 0.13 0.25 0.13 0.18 0.22 0.25 0.32 0.38 0 5 10 0 5 10
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS35007A-page 58
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
APPENDIX A: REVISION HISTORY
Version A Date 9/14/98 Revision Description This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16F8X Data Sheet, DS30430C.
APPENDIX B: CONVERSION CONSIDERATIONS
Considerations for converting from one PIC16X8X device to another are listed in Table B-1.
TABLE B-1:
CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84, PIC16F84A PIC16C84
1k x 14 36 x 8 2.0V - 6.0V (-40C to +85C) 10MHz IDD (typ) = 60A IDD (max) = 400A (LP osc, FOSC = 32kHz, VDD = 2.0V, WDT disabled) IPD (typ) = 26A IPD (max) = 100A (VDD = 2.0V, WDT disabled, industrial)
Difference
Program Memory size Data Memory size Voltage Range Maximum Operating Frequency Supply Current (IDD). See parameter # D014 in the electrical spec's for more detail. Power-down Current (IPD). See parameters # D020, D021, and D021A in the electrical spec's for more detail. Input Low Voltage (VIL). See parameters # D032 and D034 in the electrical spec's for more detail. Input High Voltage (VIH). See parameter # D040 in the electrical spec's for more detail. Data EEPROM Memory Erase/Write cycle time (TDEW). See parameter # D122 in the electrical spec's for more detail.
PIC16F83/F84
512 x 14 / 1k x 14 36 x 8 / 68 x 8 2.0V - 6.0V (-40C to +85C) 10MHz IDD (typ) = 15A IDD (max) = 45A (LP osc, FOSC = 32kHz, VDD = 2.0V, WDT disabled) IPD (typ) = 0.4A IPD (max) = 9A (VDD = 2.0V, WDT disabled, industrial)
PIC16CR83/ CR84
512 x 14 / 1k x 14 36 x 8 / 68 x 8 2.0V - 6.0V (-40C to +85C) 10MHz IDD (typ) = 15A IDD (max) = 45A (LP osc, FOSC = 32kHz, VDD = 2.0V, WDT disabled) IPD (typ) = 0.4A IPD (max) = 6A (VDD = 2.0V, WDT disabled, industrial)
PIC16F84A
1k x 14 68 x 8 2.0V - 5.5V (-40C to +125C) 20MHz IDD (typ) = 15A IDD (max) = 45A (LP osc, FOSC = 32kHz, VDD = 2.0V, WDT disabled) IPD (typ) = 0.4A IPD (max) = 9A (VDD = 2.0V, WDT disabled, industrial)
VIL (max) = 0.2VDD (Osc1, RC mode)
VIL (max) = 0.1VDD (Osc1, RC mode)
VIL (max) = 0.1VDD (Osc1, RC mode)
VIL (max) = 0.1VDD (Osc1, RC mode)
VIH (min) = 0.36VDD (I/O Ports with TTL, 4.5V VDD 5.5V)
VIH (min) = 2.4V (I/O Ports with TTL, 4.5V VDD 5.5V)
VIH (min) = 2.4V (I/O Ports with TTL, 4.5V VDD 5.5V)
VIH (min) = 2.4V (I/O Ports with TTL, 4.5V VDD 5.5V)
TDEW (typ) = 10ms TDEW (max) = 20ms
TDEW (typ) = 10ms TDEW (max) = 20ms
TDEW (typ) = 10ms TDEW (max) = 20ms
TDEW (typ) = 4ms TDEW (max) = 10ms
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 59
PIC16F84A
TABLE B-1: CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84, PIC16F84A PIC16C84
TioR, TioF (max) = 25ns (C84) TioR, TioF (max) = 60ns (LC84)
Difference
Port Output Rise/Fall time (TioR, TioF). See parameters #20, 20A, 21, and 21A in the electrical spec's for more detail. MCLR on-chip filter. See parameter #30 in the electrical spec's for more detail. PORTA and crystal oscillator values less than 500kHz
PIC16F83/F84
TioR, TioF (max) = 35ns (C84) TioR, TioF (max) = 70ns (LC84)
PIC16CR83/ CR84
TioR, TioF (max) = 35ns (C84) TioR, TioF (max) = 70ns (LC84)
PIC16F84A
TioR, TioF (max) = 35ns (C84) TioR, TioF (max) = 70ns (LC84)
No
Yes
Yes
Yes
For crystal oscillator configurations operating below 500kHz, the device may generate a spurious internal Q-clock when PORTA<0> switches state. TTL It is recommended that the EEADR<7:6> bits be cleared. When either of these bits is set, the maximum IDD for the device is higher than when both are cleared. PWRTE REXT = 3k - 100k
N/A
N/A
N/A
RB0/INT pin EEADR<7:6> and IDD
TTL/ST* (* Schmitt Trigger) N/A
TTL/ST* (* Schmitt Trigger) N/A
TTL/ST* (* Schmitt Trigger) N/A
The polarity of the PWRTE bit Recommended value of REXT for RC oscillator circuits GIE bit unintentional enable
PWRTE REXT = 5k - 100k
PWRTE REXT = 5k - 100k
PWRTE REXT = 3k - 100k
If an interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared, the GIE bit may unintentionally be re-enabled by the user's Interrupt Service Routine (the RETFIE instruction). PDIP, SOIC
N/A
N/A
N/A
Packages
PDIP, SOIC
PDIP, SOIC
PDIP, SOIC, SSOP
DS35007A-page 60
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
NOTES:
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 61
PIC16F84A
APPENDIX C: MIGRATION FROM BASELINE TO MIDRANGE DEVICES
This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a midrange device (i.e., PIC16CXXX). The following is the list of feature improvements over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and the register file (128 bytes now versus 32 bytes before). A PC latch register (PCLATH) is added to handle program memory paging. PA2, PA1 and PA0 bits are removed from the status register and placed in the option register. Data memory paging is redefined slightly. The STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions, TRIS and OPTION, are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, the Oscillator Start-up Timer (OST) and Power-up Timer (PWRT), are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change features. T0CKI pin is also a port pin (RA4/T0CKI). FSR is a full 8-bit register. "In system programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out). To convert code written for PIC16C5X to PIC16F84A, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables for reallocation. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
3. 4. 5.
2.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
DS35007A-page 62
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
INDEX A
Absolute Maximum Ratings ............................................... 41 AC (Timing) Characteristics ............................................... 47 Architecture, Block Diagram ................................................ 3 Assembler MPASM Assembler .................................................... 37 INTCON Register ........................................ 7, 10, 18, 24, 28 EEIE Bit ............................................................... 10, 29 GIE Bit ........................................................... 10, 28, 29 INTE Bit ............................................................... 10, 29 INTF Bit ............................................................... 10, 29 RBIE Bit ............................................................... 10, 29 RBIF Bit ......................................................... 10, 15, 29 T0IE Bit ................................................................ 10, 29 T0IF Bit .......................................................... 10, 18, 29 Interrupt Sources ......................................................... 21, 28 Block Diagram ........................................................... 28 Data EEPROM Write Complete ........................... 28, 31 Interrupt on Change (RB7:RB4) ................ 4, 15, 28, 31 RB0/INT Pin, External ............................... 4, 16, 28, 31 TMR0 Overflow .................................................... 18, 28 Interrupts, Context Saving During ..................................... 29 Interrupts, Enable Bits Data EEPROM Write Complete Enable (EEIE Bit) ............................................................. 10, 29 Global Interrupt Enable (GIE Bit) ............................... 10 Interrupt on Change (RB7:RB4) Enable (RBIE Bit) ................................................................... 10 RB0/INT Enable (INTE Bit) ........................................ 10 TMR0 Overflow Enable (T0IE Bit) ............................. 10 Interrupts, Flag Bits ........................................................... 28 Data EEPROM Write Complete Flag (EEIF Bit) ............................................................. 19, 29 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ....... 10 RB0/INT Flag (INTF Bit) ............................................ 10 TMR0 Overflow Flag (T0IF Bit) .................................. 10
B
Banking, Data Memory .................................................... 6, 8
C
CLKIN Pin ............................................................................ 4 CLKOUT Pin ........................................................................ 4 Code Protection ........................................................... 21, 32 Configuration Bits ............................................................... 21 Conversion Considerations ................................................ 59
D
Data EEPROM Memory ..................................................... 19 EEADR Register .................................................... 7, 24 EECON1 Register ............................................ 7, 19, 24 EECON2 Register ............................................ 7, 19, 24 EEDATA Register .................................................. 7, 24 Write Complete Enable (EEIE Bit) ....................... 10, 29 Write Complete Flag (EEIF Bit) ............................ 19, 29 Data EEPROM Write Complete ......................................... 29 Data Memory ....................................................................... 6 Bank Select (RP0 Bit) .............................................. 6, 8 Banking ........................................................................ 6 DC & AC Characteristics Graphs/Tables ........................... 53 DC Characteristics ........................................... 43, 44, 45, 46 Development Support ........................................................ 35 Development Tools ............................................................ 35
K
KeeLoq(R) Evaluation and Programming Tools .................. 38
M
Master Clear (MCLR) MCLR Pin .....................................................................4 MCLR Reset, Normal Operation ................................ 23 MCLR Reset, SLEEP .......................................... 23, 31 Memory Organization ...........................................................5 Data EEPROM Memory ............................................ 19 Data Memory ................................................................6 Program Memory ..........................................................5 Migration from Baseline to Midrange Devices ................... 62 MPLAB Integrated Development Environment Software ............................................................................ 37
E
EECON1 Register .............................................................. 19 EEIF Bit ................................................................ 19, 29 RD Bit ......................................................................... 19 WR Bit ........................................................................ 19 WREN Bit ................................................................... 19 WRERR Bit ................................................................ 19 Electrical Characteristics .................................................... 41 Endurance ............................................................................ 1 Errata ................................................................................... 2 External Power-on Reset Circuit ........................................ 25
F
Firmware Instructions ......................................................... 33 ftp site ................................................................................ 65 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) ................... 37
O
On-Line Support ................................................................ 65 OPCODE Field Descriptions ............................................. 33 OPTION_REG Register ................................. 7, 9, 16, 18, 24 INTEDG Bit ............................................................ 9, 29 PS2:PS0 Bits ......................................................... 9, 17 PSA Bit .................................................................. 9, 17 RBPU Bit ......................................................................9 T0CS Bit .......................................................................9 T0SE Bit .......................................................................9 OSC1 Pin ..............................................................................4 OSC2 Pin ..............................................................................4 Oscillator Configuration ............................................... 21, 22 HS ........................................................................ 22, 28 LP ........................................................................ 22, 28 RC ................................................................. 22, 23, 28 Selection (FOSC1:FOSC0 Bits) ................................ 21 XT ........................................................................ 22, 28
I
I/O Ports ............................................................................. 13 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 35 ID Locations ................................................................. 21, 32 In-Circuit Serial Programming (ICSP) .......................... 21, 32 Indirect Addressing ............................................................ 11 FSR Register ............................................... 6, 7, 11, 24 INDF Register ........................................................ 7, 24 Instruction Format .............................................................. 33 Instruction Set .................................................................... 33 Summary Table .......................................................... 34 INT Interrupt (RB0/INT) ...................................................... 29
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 63
PIC16F84A
P
Packaging .......................................................................... 55 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 36 PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 36 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 36 PICSTART(R) Plus Entry Level Development System ........ 35 Pinout Descriptions .............................................................. 4 Pointer, FSR ....................................................................... 11 PORTA ........................................................................... 4, 13 Initializing ................................................................... 13 PORTA Register ........................................ 7, 13, 14, 24 RA3:RA0 Block Diagram ............................................ 13 RA4 Block Diagram .................................................... 14 RA4/T0CKI Pin ................................................. 4, 13, 17 TRISA Register .................................... 7, 13, 14, 18, 24 PORTB ........................................................................... 4, 15 Initializing ................................................................... 15 PORTB Register ........................................ 7, 15, 16, 24 Pull-up Enable (RBPU Bit) ........................................... 9 RB0/INT Edge Select (INTEDG Bit) ............................. 9 RB0/INT Pin, External ...................................... 4, 16, 29 RB3:RB0 Block Diagram ............................................ 15 RB7:RB4 Block Diagram ............................................ 15 RB7:RB4 Interrupt on Change ......................... 4, 15, 29 RB7:RB4 Interrupt on Change Enable (RBIE Bit) ...... 10 RB7:RB4 Interrupt on Change Flag (RBIF Bit) .... 10, 15 TRISB Register .......................................... 7, 15, 16, 24 Power-on Reset (POR) .......................................... 21, 23, 25 Oscillator Start-up Timer (OST) ........................... 21, 25 PD Bit ............................................. 8, 23, 28, 31, 32, 34 Power-up Timer (PWRT) ..................................... 21, 25 PWRT Enable (PWRTE Bit) ....................................... 21 Time-out Sequence .................................................... 28 Time-out Sequence on Power-up ........................ 26, 27 TO Bit ....................................... 8, 23, 28, 30, 31, 32, 34 Prescaler ............................................................................ 17 Assignment (PSA Bit) ............................................ 9, 17 Block Diagram ............................................................ 18 Rate Select (PS2:PS0 Bits) ................................... 9, 17 Switching Prescaler Assignment ................................ 18 PRO MATE(R) II Universal Programmer .............................. 35 Product Identification System ............................................. 67 Program Counter ................................................................ 11 PCL Register .................................................... 7, 11, 24 PCLATH Register ............................................ 7, 11, 24 Reset Conditions ........................................................ 24 Program Memory ................................................................. 5 General Purpose Registers .......................................... 6 Interrupt Vector ...................................................... 5, 29 Reset Vector ................................................................ 5 Special Function Registers ...................................... 6, 7 Programming, Device Instructions ..................................... 33
S
Saving W Register and STATUS in RAM .......................... 29 SEEVAL(R) Evaluation and Programming System .............. 37 SLEEP ............................................................. 21, 23, 29, 31 Software Simulator (MPLAB-SIM) ..................................... 37 Special Features of the CPU ............................................. 21 Special Function Registers .............................................. 6, 7 Speed, Operating ..................................................... 1, 22, 49 Stack .................................................................................. 11 STATUS Register ................................................ 7, 8, 24, 29 C Bit ....................................................................... 8, 34 DC Bit .................................................................... 8, 34 PD Bit ............................................ 8, 23, 28, 31, 32, 34 Reset Conditions ....................................................... 24 RP0 Bit .................................................................... 6, 8 TO Bit ...................................... 8, 23, 28, 30, 31, 32, 34 Z Bit ....................................................................... 8, 34
T
Time-out (TO) Bit. See Power-on Reset (POR) Timer0 ................................................................................ 17 Block Diagram ........................................................... 17 Clock Source Edge Select (T0SE Bit) ......................... 9 Clock Source Select (T0CS Bit) .................................. 9 Overflow Enable (T0IE Bit) .................................. 10, 29 Overflow Flag (T0IF Bit) ................................ 10, 18, 29 Overflow Interrupt ................................................ 18, 29 RA4/T0CKI Pin, External Clock ................................. 17 TMR0 Register ................................................ 7, 18, 24 Timing Diagrams Diagrams and Specifications ..................................... 49 Time-out Sequence on Power-up ........................ 26, 27
W
W Register ................................................................... 24, 29 Wake-up from SLEEP ................................ 21, 25, 28, 29, 31 Interrupts ............................................................. 31, 32 MCLR Reset .............................................................. 31 WDT Reset ................................................................ 31 Watchdog Timer (WDT) ............................................... 21, 30 Block Diagram ........................................................... 30 Enable (WDTE Bit) .................................................... 21 Programming Considerations .................................... 30 RC Oscillator ............................................................. 30 Time-out Period ......................................................... 30 WDT Reset, Normal Operation .................................. 23 WDT Reset, SLEEP ............................................ 23, 31 WWW, On-Line Support ................................................ 2, 65
R
RAM. See Data Memory Reader Response .............................................................. 66 Register File ......................................................................... 6 Reset ............................................................................ 21, 23 Block Diagram ............................................................ 23 Reset Conditions for All Registers ............................. 24 Reset Conditions for Program Counter ...................... 24 Reset Conditions for STATUS Register ..................... 24 WDT Reset. See Watchdog Timer (WDT) Revision History ................................................................. 59
DS35007A-page 64
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
980106
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 65
PIC16F84A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F84A Questions: 1. What are the best features of this document? Y N Literature Number: DS35007A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS35007A-page66
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16F84A
PIC16F84A PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -XX X /XX Package XXX Pattern Examples: a) PIC16F84A -04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. PIC16LF84A - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. PIC16F84A - 20I/P = Industrial temp., PDIP package, 20MHz, normal VDD limits.
Frequency Temperature Range Range
Device Frequency Range Temperature Range Package
PIC16F84A(1), PIC16F84AT(2) PIC16LF84A(1), PIC16LF84AT(2) 04 20 blank I P SO SS = 4 MHz = 20 MHz = 0C to = -40C to +70C +85C (Commercial) (Industrial)
b)
c)
= PDIP = SOIC (Gull Wing, 300 mil body) = SSOP
Note 1: 2:
Pattern
3-digit Pattern Code for QTP, ROM (blank otherwise)
F LF T
= Standard VDD range = Extended VDD range = in tape and reel - SOIC, SSOP packages only.
(c) 1998 Microchip Technology Inc.
Preliminary
DS35007A-page 67
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835
Beijing
Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Denmark
Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Dallas
Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
11/15/99
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.

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